1. Field of the Invention
The present invention relates generally to a semiconductor memory device for a simple cache system, and more particularly, to a semiconductor memory in which a cache memory is integrated on the same chip.
2. Description of the Prior Art
In order to improve cost performance of a computer system, a small capacity and high-speed memory has been frequently provided as a high-speed buffer between a main memory structured by a low-speed, large capacity and thus, low-cost DRAM (Dynamic Random Access Memory) and a CPU (Central Processing Unit). The high-speed buffer is referred to as a cache memory. A block of data which the CPU may require is copied from the main memory and stored in the cache memory. The state in which data in an address to be accessed by the CPU exists in the cache memory is referred to as "hit". In this case, the CPU makes access to the high-speed cache memory. On the other hand, the state in which data in an address to be accessed by the CPU does not exist in the cache memory is referred to as "miss hit". In this case, the CPU makes access to the low-speed main memory and at the same time, transfers to the cache memory a block to which the data belong.
The above described cache system cannot be employed in a small-sized computer system attaching importance to the cost because it requires a high-cost and high-speed memory. Conventionally, the simple cache system has been configured utilizing a page mode and a static column mode of a general-purpose DRAM.
FIGS. 1A, 1B and 1C are timing charts showing operation timing of a normal read cycle, a page mode cycle and a static column mode cycle in the DRAM, respectively. Referring now to FIGS. 1A to 1C, the operations in the conventional DRAM will be described.
First, in the normal read cycle, a row address (RA) is acquired in a device at a falling edge of an RAS (Row Address Strobe) signal while a column address (CA) is acquired therein at a falling edge of a CAS (Column Address Strobe) signal. Data in a memory cell selected by the acquired row and column addresses (RA, CA) is outputted. Therefore, the access time requires t.sub.RAC (an RAS access time) from the falling edge of the RAS signal. A cycle time tc is the sum of a period during which the device is active and an RAS precharge period t.sub.RP. As a standard value, tc is approximately 200 ns in the DRAM with t.sub.RAC of 100 ns.
On the other hand, in the page mode and the static column mode, access is made to memory cells on the same row by changing the column address (CA). The page mode and the static column mode differ in that the column address (CA) is latched at the falling edge of the CAS signal while access is made only by the change of the column address (CA) as in an SRAM (Static Random Access Memory). Access times t.sub.CAC and t.sub.AA become values of approximately one-half of the RAS access time t.sub.RAC, i.e., approximately 50 ns, as compared with t.sub.RAS =100 ns. In addition, the cycle time is shortened. The cycle time in the page mode becomes the same value as that in the static column mode, i.e., approximately 50 ns which may differ depending on the value of the CAS precharge period t.sub.CP.
FIG. 2 is a block diagram showing basic structure of a conventional DRAM device operable in a page mode or a static column mode. A row decoder 3 selects one word line (included in a memory cell array 5) in response to a row address (RA) acquired in a row address buffer 1 at a falling edge of a RAS signal. A sense amplifier 6 detects and amplifies information in a plurality of memory cells (included in the memory cell array 5) connected to the word line through a plurality of bit lines (included in the memory cell array 5). At the time point, information corresponding to one row is latched in the sense amplifier 6. Consequently, a sense amplifier on each column is selected in response to a column address (CA), so that a page mode operation and a static column mode operation can be performed.
FIG. 3 is a diagram showing the outline of a conventional simple cache system utilizing the above described page mode (or the static column mode). FIG. 3 shows a 1 M byte memory system comprising 8 DRAM devices 22 each having 1M.times.1 structure. Thus, the number of address lines is 20 (2.sup.20 =1048576=1 M) before a row address and a column address are multiplexed. When the address lines are actually inputted to the devices, the row address and the column address are multiplexed in the direction of a time base, so that the number of address lines is 10, i.e., A.sub.0 to A.sub.8.
Referring now to a timing chart of FIG. 4, description is made on an operation of a simple cache system shown in FIG. 3. An address generator 17 generates 20 addresses of data which the CPU23 requires. A comparator 19 compares 10 addresses corresponding to the row address (RA) out of 20 addresses with a row address selected in the preceding cycle from a latch (referred to as TAG hereinafter) 18 which holds the row address. At that time, when both coincide with each other, it means that access is made on the same row as that in the preceding cycle (hit occurs), so that the comparator 19 generates a CH (Cash Hit) signal. A state machine 20 is responsive to generation of the CH signal for performing page mode control which toggles the CAS signal while holding the RAS signal at a low level. A multiplexer 21 supplies 10 column addresses (CA) to DRAM devices 22. As described above, when hit occurs, output data are obtained from the DRAM devices 22 at high speed in an access time to t.sub.CAC. Contrary to this, when the row address inputted to the comparator 19 does not coincide with the content of the TAG18, it means that access is made on a different row from that in the preceding cycle (miss hit occurs), so that the comparator 19 does not generate the CH signal. In this case, the state machine 20 performs RAS and CAS control in the normal read cycle. The address multiplexer 21 supplies to the DRAM devices 22 addresses multiplexed in the order of the row address (RA) and the column address (CA). As described above, when miss hit occurs, a normal cycle, beginning with precharging of the RAS signal is started, so that output data are obtained at low speed in an access time of t.sub.RAC. Thus, the state machine 20 generates a WAIT signal, to bring a CPU23 into a WAIT state. When miss hit occurs, a new row address is held in the TAG18.
As described in the foregoing, the conventional simple cache system is adapted such that one row (1024 bits in the case of a 1 M bit device) of the DRAM constitutes one block. In addition, only address data corresponding to one block is entered in the TAG18. Therefore, hit occurs only when data to be accessed this time is on the same row as that of data accessed last time, so that a cache hit rate is low.
Meanwhile, as another conventional example, a simple cache system disclosed in the U.S. Pat. No. 4,577,293 has been known. In this simple cache system, a register for holding data corresponding to one row is provided outside a memory cell array and data is directly extracted from this register when hit occurs, so that accessing is speeded up. However, the external register holds as one block data corresponding to one row in the memory cell array, so that a cache hit rate is low as in the conventional example shown in FIGS. 2 and 3.